By Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)
This booklet constitutes the refereed court cases of the eighth foreign Workshop on complex Parallel Processing applied sciences, APPT 2009, held in Rapperswil, Switzerland, in August 2009.
The 36 revised complete papers offered have been conscientiously reviewed and chosen from seventy six submissions. All present points in parallel and allotted computing are addressed starting from and software program concerns to algorithmic facets and complicated purposes. The papers are geared up in topical sections on structure, graphical processing unit, grid, grid scheduling, cellular software, parallel program, parallel libraries and performance.
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Additional info for Advanced Parallel Processing Technologies: 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings
E. M. Garc´ıa 20 Hammer-CMP Directory-CMP Token-CMP DiCo-CMP 4 DiCo-CV-2 DiCo-CV-4 DiCo-LP-1 DiCo-NoSC 3 2 1 Hammer-CMP Directory-CMP Token-CMP DiCo-CMP 18 16 Area Overhead (%) Memory Overhead (%) 5 DiCo-CV-2 DiCo-CV-4 DiCo-LP-1 DiCo-NoSC 14 12 10 8 6 4 2 0 0 2 4 8 16 32 64 128 256 512 1024 Number of cores (a) Overhead in terms of bits. 2 4 8 16 32 64 128 256 512 1024 Number of cores (b) Overhead in terms of area. Fig. 2. Overhead introduced by the coherence protocols evaluated in this work Directory-CMP stores the directory information either in the L2 tags, when the L2 cache holds a copy of the block, or in a distributed directory cache, when the block is stored in any of the L1 caches but not in the L2 cache.
IEEE Computer 35(2), 50–58 (2002) 16. : Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News 33(4), 92–99 (2005) 17. : SICOSYS: An integrated framework for studying interconnection network in multiprocessor systems. In: 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, January 2002, pp. 15–22 (2002) 18. 1. Technical Report HPL-2008-20, HP Labs (April 2008) 19. : UltraSPARC-III: Designing third-generation 64-bit performance.
Table 4. 0018 L1 cache L2 cache L2 directory Lightweight shared cache An Eﬃcient Lightweight Shared Cache Design for Chip Multiprocessors 6 39 Conclusions and Future Work This paper proposes an eﬃcient Lightweight Shared Cache design that applies Share Data Cache (SDC) and Victim Directory Cache (VDC) to store and manage data and directory vectors for the blocks recently cached by L1 caches in CMP. In this way, directory vectors are removed from L2 cache, thus decreasing the on-chip directory overhead and improving the scalability of CMP.